The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2009
Filed:
Aug. 03, 2006
Satoshi Kuboyama, Tsukuba, JP;
Hiroyuki Shindou, Tsukuba, JP;
Yoshiya Iide, Tsukuba, JP;
Akiko Makihara, Tsukuba, JP;
Satoshi Kuboyama, Tsukuba, JP;
Hiroyuki Shindou, Tsukuba, JP;
Yoshiya Iide, Tsukuba, JP;
Akiko Makihara, Tsukuba, JP;
Japan Aerospace Exploration Agency, Tokyo, JP;
High-Reliability Engineering & Components Corporation, Ibaraki, JP;
Abstract
Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (PPNN). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (I).