The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2009
Filed:
Oct. 13, 2006
Fumitoshi Ito, Yokohama, JP;
Fumitoshi Ito, Yokohama, JP;
SanDisk Corporation, Milpitas, CA (US);
Abstract
A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors.