The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2009
Filed:
Apr. 11, 2007
Nikolaus Bott, Villach, AT;
Oliver Haeberlen, Villach, AT;
Manfred Kotek, Villach, AT;
Joost Larik, Villach, AT;
Josef Maerz, Munich, DE;
Ralf Otremba, Kaufbeuren, DE;
Nikolaus Bott, Villach, AT;
Oliver Haeberlen, Villach, AT;
Manfred Kotek, Villach, AT;
Joost Larik, Villach, AT;
Josef Maerz, Munich, DE;
Ralf Otremba, Kaufbeuren, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.