The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2009

Filed:

Jun. 02, 2006
Applicants:

Howard Tang, San Jose, CA (US);

Fabiano Fontana, San Jose, CA (US);

David L. Rutledge, Hillsboro, OR (US);

OM P. Agrawal, Los Altos, CA (US);

Henry Law, Los Altos, CA (US);

Inventors:

Howard Tang, San Jose, CA (US);

Fabiano Fontana, San Jose, CA (US);

David L. Rutledge, Hillsboro, OR (US);

Om P. Agrawal, Los Altos, CA (US);

Henry Law, Los Altos, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic blocks and the input/output blocks. A first non-volatile memory may store user information, besides configuration data, and a first port includes a dedicated serial peripheral interface to provide access to the first non-volatile memory.


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