The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
Mar. 03, 2005
Toshiyuki Fukuda, Nagaokakyo, JP;
Masanori Minamio, Takatsuki, JP;
Hiroaki Fujimoto, Hirakata, JP;
Ryuichi Sahara, Hirakata, JP;
Kenichi Itou, Takatsuki, JP;
Toshiyuki Fukuda, Nagaokakyo, JP;
Masanori Minamio, Takatsuki, JP;
Hiroaki Fujimoto, Hirakata, JP;
Ryuichi Sahara, Hirakata, JP;
Kenichi Itou, Takatsuki, JP;
Panasonic Corporation, Osaka, JP;
Abstract
There are provided a lead frame including a plurality of first external terminal portionsprovided on a plane, inner lead portionsformed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portionsformed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor elementflip-chip bonded to the inner lead portions via bumps; and an encapsulating resinencapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin. A plurality of terminalsfor electrical connection are provided in a grid pattern in a region inside the first external terminal portions and exposed on a lower surface of the encapsulating resin. A plurality of semiconductor elements or coils and resistors can be incorporated, and further semiconductor devices can be stacked.