The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7495254 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 24, 2009

Filed:

Aug. 30, 2005
Applicants:

Jonathan R. Fales, South Burlington, VT (US);

Jerome B. Lasky, Essex Junction, VT (US);

Inventors:

Jonathan R. Fales, South Burlington, VT (US);

Jerome B. Lasky, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
Abstract

A test structure (') having an array () of test devices () for detecting and studying defects that can occur in an integrated circuit device, e.g., a transistor (), due to the relative positioning of one component () of the device with respect to another component () of the device. The test devices in the array are of a like kind, but vary in their configuration. The differences in the configurations are predetermined and selected with the intent of forcing defects to occur within at least some of the test devices. During testing, the responses of the test devices are sensed so as to determine whether or not a defect has occurred in any one or more of the test devices. If a defective test device is detected, the corresponding wafer () may be subjected to physical failure analysis for yield learning.


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