The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2009

Filed:

Jun. 29, 2005
Applicants:

Jeong-hyuk Choi, Gyeonggi-do, KR;

Wang-chul Shin, Gyeonggi-do, KR;

Jin-hyun Shin, Gyeonggi-do, KR;

Inventors:

Jeong-hyuk Choi, Gyeonggi-do, KR;

Wang-chul Shin, Gyeonggi-do, KR;

Jin-hyun Shin, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.


Find Patent Forward Citations

Choi, Jeong-hyuk. (2009). Methods of fabricating flash memory devices having a sloped trench isolation structure (U.S. Patent No. 7494868). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7494868

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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