The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2009

Filed:

Jun. 02, 2005
Applicants:

Ronald Green, San Jose, CA (US);

Sridhar Krishnan, Campbell, CA (US);

Stuart E. Wilson, Menlo Park, CA (US);

James Gill Shook, Santa Cruz, CA (US);

Ming Tsai, Sunnyvale, CA (US);

Andy Stavros, San Jose, CA (US);

Inventors:

Ronald Green, San Jose, CA (US);

Sridhar Krishnan, Campbell, CA (US);

Stuart E. Wilson, Menlo Park, CA (US);

James Gill Shook, Santa Cruz, CA (US);

Ming Tsai, Sunnyvale, CA (US);

Andy Stavros, San Jose, CA (US);

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
Abstract

An assembly is provided which includes a first circuit panel having a top surface, a first dielectric element and first conductive traces disposed on the first dielectric element. In addition, a second circuit panel has a bottom surface, a second dielectric element and second conductive traces disposed on the second dielectric element, where at least a portion of the second circuit panel overlies at least a portion of the first circuit panel. The assembly further includes an interconnect circuit panel having a third dielectric element which has a front surface, a rear surface opposite the front surface, a top end extending between the front and rear surfaces, a bottom end extending between the front and rear surfaces, and a plurality of interconnect traces disposed on the dielectric element. The bottom end of the interconnect element abuts the top surface of the first circuit panel and the top end abuts the bottom surface of the second circuit panel, where at least some of the first conductive traces are in conductive communication with the second conductive traces through the interconnect traces.


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