The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2009
Filed:
Dec. 08, 2005
Hartmut Grutzediek, Mainz, DE;
Joachim Scheerer, Mainz, DE;
Hartmut Grutzediek, Mainz, DE;
Joachim Scheerer, Mainz, DE;
PREMA Semiconductor GmbH, Mainz, DE;
Abstract
A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate for the definition of a window delimited by a peripheral edge. An N-doped well is thereupon produced in the P-doped semiconductor substrate by means of high-voltage ion implantation through the window delimited by the mask, the edge zone of said N-doped well reaching as far as the surface of the semiconductor substrate. The individual regions for the source, drain and bulk of the PMOSFET semiconductor structure are then produced in the P-doped inner zone enclosed by the well. The P-doped inner zone forms the drift zone of the PMOSFET structure. Since the drift zone has the weak basic doping of the substrate, the PMOSFET has a high dielectric strength.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile