The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2009

Filed:

Apr. 01, 2008
Applicants:

Anthony D. Polson, Jericho, VT (US);

David Lackey, Jericho, VT (US);

Theodoros E. Anemikos, Milton, VT (US);

Laura Chadwick, Essex Junction, VT (US);

Inventors:

Anthony D. Polson, Jericho, VT (US);

David Lackey, Jericho, VT (US);

Theodoros E. Anemikos, Milton, VT (US);

Laura Chadwick, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a 'schmoo plot' by varying a frequency of the clock source to determine the delay of process monitors at various locations across the chip.


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