The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Oct. 31, 2007
Greg Bakker, San Jose, CA (US);
Khaled El-ayat, Cupertino, CA (US);
Theodore Speers, San Jose, CA (US);
Limin Zhu, Fremont, CA (US);
Brian Schubert, Saratoga, CA (US);
Rabindranath Balasubramanian, Dublin, CA (US);
Kurt Kolkind, Truckee, CA (US);
Thomas Barraza, San Jose, CA (US);
Venkatesh Narayanan, San Jose, CA (US);
John Mccollum, Saratoga, CA (US);
William C. Plants, Sunnyvale, CA (US);
Greg Bakker, San Jose, CA (US);
Khaled El-Ayat, Cupertino, CA (US);
Theodore Speers, San Jose, CA (US);
Limin Zhu, Fremont, CA (US);
Brian Schubert, Saratoga, CA (US);
Rabindranath Balasubramanian, Dublin, CA (US);
Kurt Kolkind, Truckee, CA (US);
Thomas Barraza, San Jose, CA (US);
Venkatesh Narayanan, San Jose, CA (US);
John McCollum, Saratoga, CA (US);
William C. Plants, Sunnyvale, CA (US);
Actel Corporation, Mountain View, CA (US);
Abstract
A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.