The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Oct. 31, 2006
Sang H. Dhong, Austin, TX (US);
Brian Flachs, Georgetown, TX (US);
Gilles Gervais, Austin, TX (US);
Charles R. Johns, Austin, TX (US);
Brad W. Michael, Cedar Park, TX (US);
Makoto Aikawa, Tokyo, JP;
Iwao Takiguchi, Tokyo, JP;
Tetsuji Tamura, Tokyo, JP;
Sang H. Dhong, Austin, TX (US);
Brian Flachs, Georgetown, TX (US);
Gilles Gervais, Austin, TX (US);
Charles R. Johns, Austin, TX (US);
Brad W. Michael, Cedar Park, TX (US);
Makoto Aikawa, Tokyo, JP;
Iwao Takiguchi, Tokyo, JP;
Tetsuji Tamura, Tokyo, JP;
International Business Machines Corporation, Armonk, NY (US);
Abstract
In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.