The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
May. 09, 2003
David L. Roper, Austin, TX (US);
Curtis Hart, Round Rock, TX (US);
James Wilder, Austin, TX (US);
Phill Bradley, Pflugerville, TX (US);
James G. Cady, Austin, TX (US);
Jeff Buchle, Austin, TX (US);
James Douglas Wehrly, Jr., Austin, TX (US);
David L. Roper, Austin, TX (US);
Curtis Hart, Round Rock, TX (US);
James Wilder, Austin, TX (US);
Phill Bradley, Pflugerville, TX (US);
James G. Cady, Austin, TX (US);
Jeff Buchle, Austin, TX (US);
James Douglas Wehrly, Jr., Austin, TX (US);
Entorian Technologies, LP, Austin, TX (US);
Abstract
An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. The present invention may be employed to stack similar or dissimilar integrated circuits and may be used to create modularized systems. In a preferred embodiment, a die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer such as a molded plastic, for example, is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element. The integrated lower stack element may be stacked either with iterations of the integrated lower stack element or with a pre-packaged IC to create a multi-element stacked circuit module.