The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Oct. 21, 2005
Sharon Levin, Haifa, IL;
Shye Shapira, Haifa, IL;
Ira Naot, Zikhron Yaakov, IL;
Robert J. Strain, San Jose, CA (US);
Yossi Netzer, Hadera, IL;
Sharon Levin, Haifa, IL;
Shye Shapira, Haifa, IL;
Ira Naot, Zikhron Yaakov, IL;
Robert J. Strain, San Jose, CA (US);
Yossi Netzer, Hadera, IL;
Tower Semiconductor Ltd., Migdal Haemek, IL;
Abstract
A Schottky diode is formed on an isolated well (e.g., a P-well formed in a buried N-well), and utilizes cobalt silicide (CoSi) structures respectively formed on heavily doped and lightly doped regions of the isolated well to provide the Schottky barrier and backside (ohmic) contact structures of the Schottky diode. The surrounding buried N-well is coupled to a bias voltage. The Schottky barrier and backside contact structures are separated by isolation structures formed using polycrystalline silicon, which is used to form the gate structure of CMOS FETs, in order to minimize forward resistance. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.