The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2009

Filed:

Feb. 02, 2007
Applicants:

James Harnden, Hollister, CA (US);

Allen K. Lam, Fremont, CA (US);

Richard K. Williams, Cupertino, CA (US);

Anthony Chia, Singapore, SG;

Chu Weibing, Shanghai, CN;

Inventors:

James Harnden, Hollister, CA (US);

Allen K. Lam, Fremont, CA (US);

Richard K. Williams, Cupertino, CA (US);

Anthony Chia, Singapore, SG;

Chu Weibing, Shanghai, CN;

Assignee:

GEM Services, Inc., San Jsoe, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.


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