The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2009
Filed:
Jun. 16, 2006
Sabine Penka, Unterhaching, DE;
Armin Fischer, München, DE;
Sabine Penka, Unterhaching, DE;
Armin Fischer, München, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method for producing a semiconductor product. Semiconductor product components are formed in a semiconductor product region of the substrate. A layer made of low-k material is subsequently formed on the substrate. Electrically conductive interconnects are formed in and/or on the layer made of low-k material. The layer of low-k material is provided in a wiring plane of the semiconductor product region for the electrical insulation of the interconnects from one another. A grid cap region of the substrate is subjected to a spacially delimited treatment such that the value of the dielectric constant is increased in the crossover region. Accordingly, an interconnect to interconnect capacitance is formed as grid cap capacitance from the interconnects arranged in the crossover region and the material and increased value of dielectric constant. Further, the dielectric constant of the low-k material remains unchanged in the semiconductor product region.