The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2009
Filed:
Jun. 20, 2006
Jengyi Yu, San Ramon, CA (US);
Chi-i Lang, Sunnyvale, CA (US);
Judy H. Huang, Los Gatos, CA (US);
Novellus Systems, Inc., San Jose, CA (US);
Abstract
High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.