The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2009

Filed:

Dec. 21, 2005
Applicants:

Kazuhiro Satoh, Neyagawa, JP;

Kenji Shimazaki, Kobe, JP;

Takahiro Ichinomiya, Katano, JP;

Shouzou Hirano, Osaka, JP;

Inventors:

Kazuhiro Satoh, Neyagawa, JP;

Kenji Shimazaki, Kobe, JP;

Takahiro Ichinomiya, Katano, JP;

Shouzou Hirano, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.


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