The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2009

Filed:

Jun. 24, 2005
Applicants:

Suresh Chemudupati, Marlborough, MA (US);

Victor T. Lau, Marlborough, MA (US);

Bruno Diplacido, Westborough, MA (US);

Eric J. Dehaemer, Shrewsbury, MA (US);

Inventors:

Suresh Chemudupati, Marlborough, MA (US);

Victor T. Lau, Marlborough, MA (US);

Bruno DiPlacido, Westborough, MA (US);

Eric J. DeHaemer, Shrewsbury, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.


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