The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2009
Filed:
Jul. 12, 2005
David C. Scott, Santa Clara, CA (US);
Charles W. Selvidge, Wellesley, MA (US);
Joshua D. Marantz, Brookline, MA (US);
Frédéric Reblewski, Paris, FR;
David C. Scott, Santa Clara, CA (US);
Charles W. Selvidge, Wellesley, MA (US);
Joshua D. Marantz, Brookline, MA (US);
Frédéric Reblewski, Paris, FR;
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.