The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2009
Filed:
Oct. 23, 2006
Applicant:
Michio Komoda, Tokyo, JP;
Inventor:
Michio Komoda, Tokyo, JP;
Assignee:
Renesas Technology Corp., Chiyoda-Ku, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Regions Gto Geach including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A, A), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (Gto GGto G), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.