The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Jun. 30, 2005
Silvio Picano, Hillsboro, OR (US);
Sridhar Jayaraman, Portland, OR (US);
Peter Desrosier, Portland, OR (US);
James Chung, Milpitas, CA (US);
Silvio Picano, Hillsboro, OR (US);
Sridhar Jayaraman, Portland, OR (US);
Peter DesRosier, Portland, OR (US);
James Chung, Milpitas, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.