The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2009

Filed:

Dec. 30, 2005
Applicants:

Stephan J. Jourdan, Portland, OR (US);

Avinash Sodani, Hillsboro, OR (US);

Alexandre J. Farcy, Hillsboro, OR (US);

Per Hammarlund, Hillsboro, OR (US);

Sebastien Hily, Hillsboro, OR (US);

Mark C. Davis, Portland, OR (US);

Inventors:

Stephan J. Jourdan, Portland, OR (US);

Avinash Sodani, Hillsboro, OR (US);

Alexandre J. Farcy, Hillsboro, OR (US);

Per Hammarlund, Hillsboro, OR (US);

Sebastien Hily, Hillsboro, OR (US);

Mark C. Davis, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.


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