The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Mar. 15, 2004
David A. Klein, Carrollton, TX (US);
Christian L. Belady, McKinney, TX (US);
Shaun L. Harris, McKinney, TX (US);
Michael C. Day, Allen, TX (US);
Jeffrey P. Christenson, Plano, TX (US);
Brent A. Boudreaux, Highland Village, TX (US);
Stuart C. Haden, Allen, TX (US);
Eric Peterson, McKinney, TX (US);
Jeffrey N. Metcalf, Frisco, TX (US);
James S. Wells, Windsor, CO (US);
Gary W. Williams, Rowlett, TX (US);
Paul A. Wirtzberger, Greenville, TX (US);
Roy M. Zeighami, McKinney, TX (US);
Greg Huff, Plano, TX (US);
David A. Klein, Carrollton, TX (US);
Christian L. Belady, McKinney, TX (US);
Shaun L. Harris, McKinney, TX (US);
Michael C. Day, Allen, TX (US);
Jeffrey P. Christenson, Plano, TX (US);
Brent A. Boudreaux, Highland Village, TX (US);
Stuart C. Haden, Allen, TX (US);
Eric Peterson, McKinney, TX (US);
Jeffrey N. Metcalf, Frisco, TX (US);
James S. Wells, Windsor, CO (US);
Gary W. Williams, Rowlett, TX (US);
Paul A. Wirtzberger, Greenville, TX (US);
Roy M. Zeighami, McKinney, TX (US);
Greg Huff, Plano, TX (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.