The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2009

Filed:

Jul. 02, 2007
Applicants:

Vikas Agarwal, Austin, TX (US);

Sam Gat-shang Chu, Round Rock, TX (US);

Saiful Islam, Austin, TX (US);

Philip George Shephard, Iii, Round Rock, TX (US);

Inventors:

Vikas Agarwal, Austin, TX (US);

Sam Gat-Shang Chu, Round Rock, TX (US);

Saiful Islam, Austin, TX (US);

Philip George Shephard, III, Round Rock, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.


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