The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Jul. 05, 2006
Wagdi W. Abadeer, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
David M. Fried, Ithaca, NY (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Jed H. Rankin, South Burlington, VT (US);
William R. Tonti, Essex Junction, VT (US);
Wagdi W. Abadeer, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
David M. Fried, Ithaca, NY (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Jed H. Rankin, South Burlington, VT (US);
William R. Tonti, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.