The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2009

Filed:

Aug. 11, 2005
Applicants:

Jang-eun Lee, Suwon-si, KR;

Sung-lae Cho, Gwacheon-si, KR;

Jeong-hee Park, Gwangmyeong-si, KR;

Inventors:

Jang-Eun Lee, Suwon-si, KR;

Sung-Lae Cho, Gwacheon-si, KR;

Jeong-Hee Park, Gwangmyeong-si, KR;

Assignee:

Samsung Electronics Co., Ltd, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on a semiconductor substrate. A molding insulating layer is formed on the conductive layer and a via hole is formed through the insulating layer to expose a region of the conductive layer. A first via filling layer is formed and then partially removed to form a partial via plug. The formation and removal of the phase change material layer are then repeated as necessary to form a multilayer plug structure that substantially fills the via hole with the multilayer structure typically exhibiting reduced defects and damage than plug structures prepared by conventional methods.


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