The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Dec. 26, 2007
Jae-seong Byun, Suwon, KR;
Kun-jong Lee, Seoul, KR;
Hyun-su Lim, Suwon, KR;
Jong-hwan Cha, Kyungki-do, KR;
Bae-hyoun Jung, Yongin, KR;
Jae-Seong Byun, Suwon, KR;
Kun-Jong Lee, Seoul, KR;
Hyun-Su Lim, Suwon, KR;
Jong-Hwan Cha, Kyungki-do, KR;
Bae-Hyoun Jung, Yongin, KR;
Samsung Electronics., Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on the insulating substrate. The gate wire includes a gate line and a gate pad connected to one end of the gate line. A gate insulating layer is formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad. A semiconductor pattern is formed on the gate insulating layer. A data wire is formed on the gate insulating layer. The data wire includes a data line, a source electrode connected to the data line, a drain electrode facing the source electrode and a data pad connected to one end of the data line. A passivation layer is formed on the gate insulating layer while exposing the data pad and a portion of the data line close to the data pad.