The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2008
Filed:
Aug. 11, 2006
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design. The netlist and an identification of each tile are input. For each of the tiles, a specification is input of a graphical tile representation and connection representations that terminate at a boundary of the tile representation. A specification is input of an arrayed placement of occurrences of the tile representations. For each abutting pair of occurrences of the tile representations in the arrayed placement, the connection representations are determined that terminate at a shared portion of the boundaries of the tile representations of the abutting pair. For each of a plurality of positions within the shared portion of the boundaries of the tile representations of each abutting pair, a match is checked between the connection representations terminating at the position.