The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2008
Filed:
Dec. 15, 2006
Christopher V. Baiocco, Newburgh, NY (US);
Xiangdong Chen, Poughquag, NY (US);
Young G. Ko, Fishkill, NY (US);
Melanie J. Sherony, Fishkill, NY (US);
Christopher V. Baiocco, Newburgh, NY (US);
Xiangdong Chen, Poughquag, NY (US);
Young G. Ko, Fishkill, NY (US);
Melanie J. Sherony, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.