The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2008
Filed:
Nov. 04, 2005
Edward J. Nowak, Essex Junction, VT (US);
Bethann Rainey, Burlington, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
BethAnn Rainey, Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A finFET () having sidwall spacers () to suppress parasitic devices in the upper region of a channel and at the bases of source(s) and drain(s) that are artifacts of the fabrication techniques used to make the finFET. The FinFET is formed on an SOI wafer () by etching through a hardmask () so as to form a freestanding fin (). Prior to doping the source(s) () and drain(s) (), a layer () of thermal oxide is deposited over the entire finFET. This layer is etched away so as to form the sidewall spacers at each reentrant corner formed where a horizontal surface meets a vertical surface. Sidewall spacers () inhibit doping of the upper region of source(s) and drain(s) immediately adjacent the gate. Sidewall spacers () fill in any undercut regions () of BOX layer () that may have been formed during prior fabrication steps.