The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2008
Filed:
Nov. 30, 2005
Ercan Adem, Sunnyvale, CA (US);
Matthew Buynoski, Palo Alto, CA (US);
Robert Chiu, San Jose, CA (US);
Bryan Choo, Mountain View, CA (US);
Calvin Gabriel, Cupertino, CA (US);
Joong Jeon, Cupertino, CA (US);
David Matsumoto, San Jose, CA (US);
Jeffrey Shields, Sunnyvale, CA (US);
Bhanwar Singh, Morgan Hill, CA (US);
Winny Stockwell, Redwood City, CA (US);
Wen Yu, Fremont, CA (US);
Ercan Adem, Sunnyvale, CA (US);
Matthew Buynoski, Palo Alto, CA (US);
Robert Chiu, San Jose, CA (US);
Bryan Choo, Mountain View, CA (US);
Calvin Gabriel, Cupertino, CA (US);
Joong Jeon, Cupertino, CA (US);
David Matsumoto, San Jose, CA (US);
Jeffrey Shields, Sunnyvale, CA (US);
Bhanwar Singh, Morgan Hill, CA (US);
Winny Stockwell, Redwood City, CA (US);
Wen Yu, Fremont, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Advanced Micro Devices Inc., Sunnyvale, CA (US);
Abstract
In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.