The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2008

Filed:

Jul. 27, 2005
Applicants:

Hormuzd M. Khosravi, Portland, OR (US);

Uday Savagaonkar, Beaverton, OR (US);

Ravi Sahita, Beaverton, OR (US);

Priya Rajagopal, Wharton, NJ (US);

Inventors:

Hormuzd M. Khosravi, Portland, OR (US);

Uday Savagaonkar, Beaverton, OR (US);

Ravi Sahita, Beaverton, OR (US);

Priya Rajagopal, Wharton, NJ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a method, system, program and device for maintaining shadow page tables in a sequestered memory region. A first processor executing an application invokes a second processor to create a shadow page table used for address translation for the application in a sequestered memory region non-alterable by processes controlled by an operating system executed by the first processor. The shadow page table references at least one page in an operating system memory region accessible to processes controlled by the operating system.


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