The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2008
Filed:
Jun. 20, 2006
Adrian E. Ong, Pleasanton, CA (US);
Naresh Baliga, El Dorado, CA (US);
Chiate Lin, San Jose, CA (US);
Adrian E. Ong, Pleasanton, CA (US);
Naresh Baliga, El Dorado, CA (US);
Chiate Lin, San Jose, CA (US);
Inapac Technology, Inc., San Jose, CA (US);
Abstract
A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit to transition between normal operation and the test mode.