The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2008
Filed:
Sep. 07, 2005
Xiaolin Chen, San Jose, CA (US);
Srinivas D. Nemani, Sunnyvale, CA (US);
Dongqing LI, Fremont, CA (US);
Jeffrey C. Munro, Santa Clara, CA (US);
Marlon E. Menezes, Mountain View, CA (US);
Xiaolin Chen, San Jose, CA (US);
Srinivas D. Nemani, Sunnyvale, CA (US);
DongQing Li, Fremont, CA (US);
Jeffrey C. Munro, Santa Clara, CA (US);
Marlon E. Menezes, Mountain View, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.