The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2008
Filed:
May. 25, 2005
Peijun Jerry Chen, Dallas, TX (US);
Tsai Wilman, Saratoga, CA (US);
Mathieu Caymax, Leuven, BE;
Jan Willem Maes, Wilrijk, BE;
Peijun Jerry Chen, Dallas, TX (US);
Tsai Wilman, Saratoga, CA (US);
Mathieu Caymax, Leuven, BE;
Jan Willem Maes, Wilrijk, BE;
Interuniversitair Microelektronica Centrum vzw, Leuven, BG;
ASM America Inc., Phoenix, AZ (US);
Abstract
The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.