The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
Feb. 15, 2006
Jung-woo Seo, Suwon-si, KR;
Jong-seo Hong, Yongin-si, KR;
Tae-hyuk Ahn, Yongin-si, KR;
Jeong-sic Jeon, Hwaseong-si, KR;
Jun-sik Hong, Yongin-si, KR;
Young-sun Cho, Suwon-si, KR;
Jung-woo Seo, Suwon-si, KR;
Jong-seo Hong, Yongin-si, KR;
Tae-hyuk Ahn, Yongin-si, KR;
Jeong-sic Jeon, Hwaseong-si, KR;
Jun-sik Hong, Yongin-si, KR;
Young-sun Cho, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.