The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2008

Filed:

Aug. 14, 2006
Applicants:

Nobuya Koike, Tokyo, JP;

Tsukasa Matsushita, Tokyo, JP;

Hiroshi Sato, Tokyo, JP;

Keiichi Okawa, Tokyo, JP;

Atsushi Nishikizawa, Tokyo, JP;

Inventors:

Nobuya Koike, Tokyo, JP;

Tsukasa Matsushita, Tokyo, JP;

Hiroshi Sato, Tokyo, JP;

Keiichi Okawa, Tokyo, JP;

Atsushi Nishikizawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/111 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross-section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire


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