Ic functional and delay fault testing

Abstract

An integrated circuit (IC) tester tests an IC having logic blocks that communicate through clocked devices arranged into scan chains. The tester organizes a low-speed IC functional test into a succession of test cycles, each of a uniform test cycle period, and can clock each clocked device up to once per test cycle with adjustable clock signal edge timing. At selected times during the functional test, the tester executes a capture procedure wherein it adjusts clock signal edge timing so that a delay between clocking of the input and output signals of selected logic blocks is less than the test cycle period to determine whether those logic blocks can operate at high frequency without delay faults. The tester executes a scan procedure immediately following each capture procedure to acquire data representing states of logic block output signals to enable the tester to determine whether one or more selected logic blocks experienced delay faults during the capture procedure.