Programmable logic devices with distributed memory

Abstract

A programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide distributed random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure. In one embodiment, there are at least twice as many logic blocks in the first plurality of logic blocks than in the second plurality of logic blocks. In another embodiment, the first and second plurality of logic blocks are arranged in one or more rows, and the programmable logic device includes one or more rows of embedded block RAM.