The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Apr. 05, 2006
Howard Tang, San Jose, CA (US);
Henry Law, Los Altos, CA (US);
David L. Rutledge, Hillsboro, OR (US);
OM P. Agrawal, Los altos, CA (US);
Fabiano Fontana, San Jose, CA (US);
Howard Tang, San Jose, CA (US);
Henry Law, Los Altos, CA (US);
David L. Rutledge, Hillsboro, OR (US);
Om P. Agrawal, Los altos, CA (US);
Fabiano Fontana, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.