Electric circuit and test apparatus for outputting a recovered clock input signal

Abstract

There is provided an electric circuit that outputs a timing signal and a recovered clock. The electric circuit includes a delay circuit that delays a reference signal, a PLL section that delays an oscillation signal synchronized with the delayed reference signal by an offset delay amount to output the delayed oscillation signal when outputting the timing signal and changes a delay amount for the oscillation signal in a tracking range using the offset delay amount as a standard to output the oscillation signal in synchronization with a periodic signal when outputting the recovered clock, a delay amount separating section that separates a coarse component of an integral multiple of a period of the clock signal and a fine component less than the period of the clock signal from a system timing, and a delay setting section that sets a value obtained by subtracting an adjusted delay amount, which is an integral multiple of the period of the clock signal, from the coarse component as the delay amount of the delay circuit and sets a value obtained by adding the adjusted delay amount to the fine component as the offset delay amount if the tracking range in a negative direction is larger than the fine component.