The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2008

Filed:

Mar. 20, 2006
Applicants:

Hiroaki Niimi, Dallas, TX (US);

Reima Tapani Laaksonen, Dallas, TX (US);

Inventors:

Hiroaki Niimi, Dallas, TX (US);

Reima Tapani Laaksonen, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region. The method further includes subjecting exposed portions of the first layer of gate dielectric material to a nitrogen containing plasma, thereby forming a second layer of gate dielectric material over the first layer of gate dielectric material located in the first active region, incorporating oxygen into the second layer of gate dielectric material located in the first active region, and removing the, patterned masking layer, thereby resulting in a first greater thickness gate dielectric in the first active region and a second lesser thickness gate dielectric in the second active region.


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