The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2008
Filed:
Feb. 24, 2006
Applicants:
Atsunori Hirobe, Tokyo, JP;
Toru Ishikawa, Tokyo, JP;
Inventors:
Atsunori Hirobe, Tokyo, JP;
Toru Ishikawa, Tokyo, JP;
Assignee:
Elpida Memory, Inc., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01); G05F 3/02 (2006.01);
U.S. Cl.
CPC ...
Abstract
A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.
Hirobe, Atsunori. (2008). Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit (U.S. Patent No. 7456681). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7456681
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile