The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2008

Filed:

Feb. 09, 2006
Applicants:

Thomas W. Dyer, Pleasant Valley, NY (US);

Xiangdong Chen, Poughquag, NY (US);

James J. Toomey, Poughkeepsie, NY (US);

Haining S. Yang, Wappingers Falls, NY (US);

Inventors:

Thomas W. Dyer, Pleasant Valley, NY (US);

Xiangdong Chen, Poughquag, NY (US);

James J. Toomey, Poughkeepsie, NY (US);

Haining S. Yang, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.


Find Patent Forward Citations

Dyer, Thomas. (2008). Cmos devices with hybrid channel orientations and method for fabricating the same (U.S. Patent No. 7456450). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7456450

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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