The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2008

Filed:

Mar. 30, 2007
Applicants:

Alan S. Chen, Windermere, FL (US);

Mark Dyson, Singapore, SG;

Nace M. Rossi, Singapore, SG;

Ranbir Singh, Singapore, SG;

Xiaojun Yuan, Singapore, SG;

Inventors:

Alan S. Chen, Windermere, FL (US);

Mark Dyson, Singapore, SG;

Nace M. Rossi, Singapore, SG;

Ranbir Singh, Singapore, SG;

Xiaojun Yuan, Singapore, SG;

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.


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