The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7454733 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 18, 2008

Filed:

Mar. 06, 2002
Applicants:

Amir Alon, Ramat Ishai, IL;

David Goren, Nesher, IL;

Rachel Gordin, Hadera, IL;

Betty Livshitz, Qiriat Yam, IL;

Anatoly Sherman, Haifa, IL;

Michael Zelikson, Haifa, IL;

Inventors:

Amir Alon, Ramat Ishai, IL;

David Goren, Nesher, IL;

Rachel Gordin, Hadera, IL;

Betty Livshitz, Qiriat Yam, IL;

Anatoly Sherman, Haifa, IL;

Michael Zelikson, Haifa, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.


Find Patent Forward Citations

Alon, Amir. (2008). Interconnect-aware methodology for integrated circuit design (U.S. Patent No. 7454733). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7454733

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