The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

Oct. 18, 2005
Applicants:

Kenneth S. Mcelvain, Los Altos, CA (US);

Robert Erickson, Cupertino, CA (US);

Inventors:

Kenneth S. McElvain, Los Altos, CA (US);

Robert Erickson, Cupertino, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a hierarchical resource estimation is performed based on a technology independent register transfer level (RTL) netlist, which is to be partitioned between multiple ICs. Based on the estimation, the RTL netlist is partitioned between the multiple ICs. In response to the partition and the estimation, immediate feedback information is provided to a user.


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