The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

Feb. 11, 2005
Applicant:

Jenoe Tihanyi, Kirchheim, DE;

Inventor:

Jenoe Tihanyi, Kirchheim, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a circuit arrangement having connecting terminals (K, K) for application of a supply voltage (V+) and having a load transistor (M) for connecting a load (Z) to the supply voltage, said load transistor having a control terminal (G) and a first and second load terminal (D, S), the control terminal (G) of the load transistor () being coupled to a drive terminal (IN) for application of a drive signal (Sin). A voltage limiting circuit () is connected between one (D) of the load terminals and the drive terminal (G) of the transistor, a deactivation circuit () being provided, which is designed to deactivate the voltage limiting circuit () in a manner dependent on the supply voltage (V+).


Find Patent Forward Citations

Tihanyi, Jenoe. (2008). Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor (U.S. Patent No. 7453308). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7453308

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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