The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

Nov. 10, 2006
Applicants:

Wei-zhe Wong, Tainan, TW;

Ching-sung Yang, Hsinchu, TW;

Chih-chen Cho, Taipei, TW;

Inventors:

Wei-Zhe Wong, Tainan, TW;

Ching-Sung Yang, Hsinchu, TW;

Chih-Chen Cho, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8247 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.


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